1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to semiconductor memory devices with antifuses.
2. Description of the Related Art
As the number of electronic elements contained on semiconductor integrated circuits continues to increase, the problem of reducing and eliminating defects in the elements becomes more difficult. To achieve higher population capacities, circuit designs strive to reduce the size of the individual elements to maximize available die real estate. The reduced size, however, makes these elements increasingly more susceptible to defects. These defects can be identified upon completion of the integrated circuits by testing procedures at the semiconductor chip level. Scraping or discarding defective circuits is economically undesirable, particularly if only a small number of elements are actually defective.
To reduce the amount of semiconductor scrap, therefore, redundant elements are provided on the circuit. If a primary element is determined to be defective, a redundant element can be substituted for the defective element. Substantial reductions in scrap can be achieved by using redundant elements.
One type of integrated circuit device that uses redundant elements is semiconductor memory, such as a dynamic random access memory (DRAM). 64 Mbit, 128 Mbit, 256 Mbit and 512 Mbit DRAMs are available in the market. Typical DRAM circuits comprise millions of equivalent memory cells arranged in addressable rows and columns. With redundant elements, either as rows or columns, defective primary rows and columns can be replaced. Thus, using redundant elements reduces scrap without substantially increasing the cost of the memory circuit.
Because the individual primary elements of a memory are separately addressable, replacing a defective element typically comprises selecting a bank of switch circuits, each switch circuit typically being an antifuse circuit, respectively, to ‘program’ a redundant element to respond to the address of the defective element, and then enabling the redundant element by programming to enable antifuse circuit.
U.S. Pat. No. 6,249,472 B1 issued Jan. 19, 2001 to Tamura et al., which corresponds to JP H11-191614 A, shows a semiconductor memory device whose antifuse can be formed without any additional film forming process.
With reference to FIGS. 6-8, the known technique according to U.S. Pat. No. 6,249,472 B1 of forming antifuses without any additional film forming process is implemented. FIG. 6 is a cross sectional view of a portion of a semiconductor memory device, showing a MOS transistor 10 coupled to an antifuse 20. The MOS transistor 10 includes a gate 1, a source 2 and a drain 3. FIG. 7 is a cross sectional view of another portion of the semiconductor memory device, showing a memory cell 50 including a capacitor 40 and a MOS transistor 30. The MOS transistor 30 includes a gate 11, a source 12 and a drain 13.
The sources 2 and 12 are diffused regions, which are formed in a semiconductor substrate concurrently. Similarly, the drains 3 and 13 are diffused regions, which are formed in the semiconductor substrate concurrently. The gates 1 and 11 are formed on the semiconductor substrate, concurrently.
As shown in FIG. 7, the capacitor 40 of the memory cell 50 includes one portion 14 of a dielectric layer. As shown in FIG. 6, the antifuse 20 includes another or second portion 105 of the same dielectric layer. This dielectric layer is formed in the conventional deposition process, and etched to provide the dielectric layer portions 15 and 105 concurrently.
In FIG. 7, the capacitor 40 includes a capacitor first electrode 14 that is a first portion of a first conductive layer. The first conductive layer is formed on one side surface of the dielectric layer. The capacitor 40 also includes a capacitor second electrode 16 that is a first portion of a second conductive layer. The second conductive layer is formed on the opposite side surface of the dielectric layer. The capacitor electrodes 14 and 16, which may be called as capacitor lower and upper electrodes, respectively, have interposed therebetween the capacitor dielectric layer portion 15.
In FIG. 6, the antifuse 20 includes an antifuse first electrode 104 that is a second portion of the above-mentioned first conductive layer. The antifuse 20 also includes an antifuse second electrode 106 that is a second portion of the above-mentioned second conductive layer. The electrodes 104 and 106, which may be called as antifuse lower and upper electrodes, respectively, have interposed therebetween the antifuse dielectric layer portion 105.
The above-mentioned first conductive layer is formed in the conventional CMOS process, and etched to provide the capacitor and antifuse electrodes 14 and 104 concurrently. Similarly, the above-mentioned second conductive layer is formed in the conventional CMOS process, and etched to provide the capacitor and antifuse electrodes 16 and 106 concurrently.
In FIG. 7, the capacitor lower electrode 14 is electrically connected via a conductor plug to the drain 13 of the MOS transistor 30. The source 12 of the MOS transistor 30 is electrically connected via a conductor plug to a digit line 17.
In FIG. 6, the antifuse lower electrode 104 is electrically connected via a conductor plug to the drain 3 of the MOS transistor 10. The source 2 of the MOS transistor 10 is electrically connected via a conductor plug to a ground level potential electrode 7, which is held at ground potential VGND. The antifuse upper electrode 106 is electrically connected via a conductor plug to an upper potential level electrode 8, which may be connected to a power source having power source voltage VDD or an antifuse enabling power source having breakdown voltage. The breakdown voltage is higher than the power source voltage VDD.
FIG. 8 is an antifuse circuit corresponding to FIG. 6. In the illustrated antifuse circuit, the power source voltage VDD is applied to the electrode 8 with the electrode 7 grounded so that the difference in potential across the electrodes 8 and 7 may be expressed as VDD−VGND.
If the dielectric layer portion 105 of the antifuse 20 is not punctured yet, the output VOUT at an output terminal 60 is equal to the ground potential VGND when the MOS transistor 10 is conductive. The ground potential VGND may be considered as high as 0 volt (VGND=0 volt). Thus, the output VOUT at the output terminal 60 is 0 volt. Under this condition, the power source voltage VDD may be applied to the dielectric layer portion 105 of the antifuse 20.
The dielectric layer portion 105 of the antifuse 20 is punctured when, with the MOS transistor 10 conductive, the breakdown voltage is applied. After the dielectric layer portion 105 has been punctured to short the antifuse lower and upper electrodes 104 and 106 of the antifuse 20, the output at the output terminal 60 is equal to the power source voltage VDD when the MOS transistor 10 is conductive.
As mentioned before, applying the breakdown voltage to the antifuse shorts an antifuse associated with a redundant circuit that is to substitute a defective circuit. Thus, the occurrence of such substitution of the defective circuit can be determined by examining the level of the output VOUT at the output terminal 60.
To maximize available die real estate, circuit designs strive to reduce the size of the individual memory cells. Taking the semiconductor memory device in FIGS. 6 and 7 as an example, reduction in size of each capacitor 40 without any reduction in its capacity is required. The reduced size inevitably results in reduced area of the capacitor dielectric layer portion 15, causing the capacity to reduce. The capacity is proportional to the area, but it is inversely proportional to the thickness. Thinning the capacitor dielectric layer portion 15 is important in suppressing the reduction in capacity accompanying the size reduction of the individual memory cells.
As the thickness reduces, the breakdown voltage of the capacitor dielectric layer portion 15 drops. Applying the power source voltage VDD as it is to the individual memory cells limits thinning the dielectric layer portion 15. Recently, it is the prevailing practice to apply one half (½) of VDD to the individual memory cells. This practice makes great contribution to maintaining the required capacity needed for the size reduction of the memory cells.
As mentioned before, the dielectric layer portion 105 of the antifuse 20 and the dielectric layer portion 15 of the memory cell 50 are formed out of the same dielectric layer. Thus, the dielectric layer portions 105 and 15 are of the same thickness.
If, here, the antifuse circuit in FIG. 8 is used, the dielectric layer portion 105 may be subjected to power source voltage VDD during normal operation of the memory device. As it is formed concurrently with the capacitor 40 of the memory device (DRAM) in the same fabrication processes, the antifuse 20 has potential problem that its component might be deteriorated by application of power source voltage VDD and in the fatal case the dielectric layer portion 105 might be punctured.
Thus, a need remains for a semiconductor memory device with a reliable antifuse.
The following three sections provide description on the prior art, which involves JP P2000-123592 A (=U.S. Pat. No. 6,115,283 issued Sep. 5, 2000 to Hidaka, U.S. Pat. No. 6,469,923 B1 issued Oct. 22, 2002 to Hidaka), JP P2001-28397 A and JP H08-316324 A.
JP P2000-123592 A discloses a semiconductor memory device with capacitor-type antifuses arranged in rows and columns within a peripheral region. The capacitor-type antifuses are connected in parallel. They are of the same configuration as capacitors of memory cells and fabricated within the peripheral region using the same pattern as used in fabricating the memory cells.
JP P2001-28397 A discloses a semiconductor device in the form of a field programmable gate array (FPGA). The FPGA includes a lower wiring layer formed on a semiconductor substrate, an antifuse layer on the lower electrode, an etch stop layer on the antifuse layer, and an interlayer dielectric layer. A conductor plug fills a via-hole formed through the interlayer dielectric layer. At one end, the conductor plug is connected to the etch stop layer. At the opposite end, the conductor plug is connected to an upper wiring formed on the interlayer dielectric layer.
JP H08-316324 discloses a method of fabricating a semiconductor device. According to this method, an antifuse is formed together with a metal-insulator-semiconductor field effect transistor (MISFET) sharing a hole forming process and an electrode forming process. A connection hole between lower and upper electrodes of an antifuse and a connection hole for wiring a MISFET are formed in the same process. The lower electrode and a source/drain of the MISFET are formed in the same process.